`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 			Arizona State University
// Engineer: 			Joe Boeding
// 						Taylor Wood
//
// Create Date:    	14:44:55 04/01/2013 
// Design Name: 		switch_latcher
// Module Name:    	tb_switch_latcher
// Project Name: 		LAB #2
// Target Devices: 	Xilinx Spartan6 XC6LX16-CS324
// Tool versions: 	Xilinx ISE 14.2
// Description: 		
//		Test bench for switch_latcher
//
// Dependencies: 		switch_latcher.v
//
// Revision: 		
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module tb_switch_latcher;
	 
	// Inputs
	reg i_switch;
	reg i_clk;
	reg i_resetb;

	reg [2:0] test_case = 1'd0;

	// Outputs
	wire o_latched_data;

	// Instantiate the Unit Under Test (UUT)
	switch_latcher uut (
		.i_switch(i_switch), 
		.i_clk(i_clk), 
		.i_resetb(i_resetb), 
		.o_latched_data(o_latched_data)
	);

	//clock generator
	initial begin
		i_clk = 1'b0;
		forever #5 i_clk = ~i_clk;
	end
	initial begin
		// Initialize Inputs
		i_switch = 0;
		i_resetb = 0;
		test_case =0;
		
		// Wait 100 ns for global reset to finish
		#100;
		
		//Test Case 1 
		//	Sc. (Switch while Reset)
		//	Ex. (Output always low)
		test_case = 1;
		i_switch = 1;
		#3000000;
		
		//Test Case 2
		//	Sc. (Switch while no reset)
		// Ex. (Output high after 120000 cycles)
		test_case = 2;
		i_resetb = 1;
		#3000000;
		
		//Test Case 3
		// Sc. (Glitch Test off)
		// Ex. (No change in output)
		test_case = 3;
		i_switch = 0;
		#1200000;
		i_switch = 1;
		#3000000;

		//Test Case 4
		// Sc. (Switch release)
		// Ex. (No output after 240000 cycles)
		test_case = 4;
		i_switch = 0;
		#3000000;
		
		//Test Case 5
		// Sc. (Glitch Test on)
		// Ex. (No change in output)
		test_case = 5;
		i_switch = 1;
		#700000;
		i_switch = 0;
		#3000000;
 
		//End Testing
		test_case = 0;
	end
	

endmodule

